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专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1nsmodule count_module(input clk,input rst_n,output reg [5:0]second,output reg [5:0]minute);always @ (posedge clk or negedge rst_n) begin if (~rst_n) second <= 0 ; else if (minute >= 60) second <= 0 ;else second <= (second == 60) ? 1 : second + 1 ; endalways @ (posedge clk or negedge rst_n) begin if (~rst_n) minute <= 0 ; else begin if (minute >= 60) minute <= 0 ; else if (second == 60) minute <= minute + 1 ; else minute <= minute ; endendendmodule